Technical Questions On Computer Architecture and Design

1. What is pipelining? 2. What are the five stages in a DLX pipeline? 3. For a pipeline with ‘n’ stages, what’s the ideal throughput? What prevents us from achieving this ideal throughput? 4. What are the different hazards? How do you avoid them? 5. Instead of just 5-8 pipe stages why not have, say, a pipeline with 50 pipe stages? 6. What are Branch Prediction and Branch Target Buffers? 7. How do you handle precise exceptions or interrupts? 8. What is a cache? 9. What’s the difference between Write-Through and Write-Back Caches? Explain advantages and disadvantages of each. 10. Cache Size is 64KB, Block size is 32B and the cache is Two-Way Set Associative. For a 32-bit physical address, give the division between Block Offset, Index and Tag. 11. What is Virtual Memory? 12. What is Cache...

Read more »